The fabrication of integrated circuits includes many diverse processing steps. One of the operations frequently employed is the deposition of a dielectric film into a gap between features patterned over or into silicon substrates. One of the goals in depositing such material is to form a void-free, seam-free fill in the gap. As device dimensions become smaller in the context of DRAM, flash memory and logic, for example, it has become increasingly difficult to achieve this type of ideal fill.
While deposition methods such as high density plasma (HDP), sub-atmospheric chemical vapor deposition (SACVD), and low pressure chemical vapor deposition (LPCVD) have been used for gap fill, these methods do not achieve the desired fill capability. Flowable chemical vapor deposition and spin-on dielectric (SOD) methods can achieve the desired fill, but tend to deposit highly porous films. Further, these methods are especially complex and costly to integrate, as they require many extra processing steps. Atomic layer deposition (ALD) processes have also been used for gap fill, but these processes suffer from long processing times and low throughput, especially for large gaps. In some cases, multi-step deposition processes are used, including deposition-etch-deposition processes which require distinct etching operations between subsequent deposition operations. The etching may be done to remedy or prevent void formation in the gap. While this method is useful, it would be preferable to use a process that involves only deposition, with no required etch operations.
A further challenge is simultaneously filling gaps of different sizes on a substrate. For example, a deposition method optimized for a wide gap with a small aspect ratio may not be suitable for filling a narrow gap with a large aspect ratio, and vice versa. Therefore, a method of achieving void-free, seam-free fill of dielectric material into a gap is needed, particularly one that may be used to simultaneously fill gaps of various sizes.